Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2019-10-28 | Linux: Fix compilation error if type __u64 is already defined by gcc | Mounir IDRASSI | 1 | -5/+3 | |
This is the case with Mageia Cauldron which has gcc 9.2.1 | |||||
2019-10-24 | Linux/MacOSX: Better approach to avoid that jitterentropy code is optimized ↵ | Mounir IDRASSI | 1 | -1/+5 | |
by the compiler | |||||
2019-10-23 | Linux/MacOSX: Add missing JitterEntropy implementation | Mounir IDRASSI | 1 | -4/+13 | |
2019-10-17 | Linux: Workaround for gcc 4.4.7 bug under CentOS 6 that causes VeraCrypt ↵ | Mounir IDRASSI | 1 | -0/+14 | |
built under CentOS 6 to crash when Whirlpool hash is used. | |||||
2019-10-04 | Fix "error "SSSE3 instruction set not enabled" when compiling using GCC ↵ | El Mostafa Idrassi | 1 | -0/+2 | |
version < 4.9 without -mssse3 option (SSSE3=1 when using make). (#507) Compiling with -mxxx defines the corresponding macro of the intrinsics. For example, -mssse3 defines __SSSE3__ macro to 1. In GCC versions < 4.9, it is not possible to use and call x86 intrinsics only at runtime without compiling the entire file with the -mxxx option. For example, if we want to call SSSE3 intrinsics without compiling with -mssse3, the macro __SSSE3__ is not defined. Therefore, when including <tmmintrin.h>, this results in "error "SSSE3 instruction set not enabled"" because of : #ifndef __SSSE3__ # error "SSSE3 instruction set not enabled" Since GCC 4.9, this has been fixed and it is possible to call x86 intrinsics from select functions in a file that are tagged with the corresponding target attribute without having to compile the entire file with the -mxxx option. This can be seen in <tmmintrin.h> which in recent versions (>= 4.9) contains : #ifndef __SSSE3__ #pragma GCC push_options #pragma GCC target("ssse3") #define __DISABLE_SSSE3__ Since SSSE3 is only used under Windows for ChaCha256, this can be fixed by preceding '#include <tmmintrin.h>' with #if defined (_MSC_VER) && !defined (TC_WINDOWS_BOOT). See https://gcc.gnu.org/gcc-4.9/changes.html | |||||
2019-10-02 | Align section types of Whirlpool_C and SHA256_K (#479) | Hans-Peter Jansen | 1 | -1/+1 | |
in order to fix LTO linking. After switching to LTO for openSUSE Tumbleweed, veracrypt build failed with: [ 185s] ../Crypto/Whirlpool.c:105:45: error: 'Whirlpool_C' causes a section type conflict with 'SHA256_K' [ 185s] 105 | CRYPTOPP_ALIGN_DATA(16) static const uint64 Whirlpool_C[8*256+R] CRYPTOPP_SECTION_ALIGN16 = { [ 185s] | ^ [ 185s] ../Crypto/Sha2.c:321:34: note: 'SHA256_K' was declared here [ 185s] 321 | CRYPTOPP_ALIGN_DATA(16) uint_32t SHA256_K[64] CRYPTOPP_SECTION_ALIGN16 = { [ 185s] | ^ [ 185s] lto-wrapper: fatal error: g++ returned 1 exit status Aligning section types of Whirlpool_C and SHA256_K fixes this. | |||||
2019-08-26 | Windows: fix compilation error of legacy MBR bootloader caused by missing ↵ | Mounir IDRASSI | 1 | -1/+1 | |
intrin.h header | |||||
2019-03-21 | Linux: Fix compilation error caused by wrong include of "intrin.h" | Mounir IDRASSI | 1 | -3/+1 | |
2019-03-02 | Windows: Generalize RAM encryption for keys to VeraCrypt binaries, ↵ | Mounir IDRASSI | 2 | -0/+24 | |
especially Format and Expander | |||||
2019-03-01 | Windows: Implement RAM encryption for keys on 64-bit machines using ChaCha12 ↵ | Mounir IDRASSI | 7 | -0/+1852 | |
cipher and t1ha non-cryptographic fast hash (https://github.com/leo-yuriev/t1ha) | |||||
2019-02-12 | Windows: Use Hardware RNG based on CPU timing jitter "Jitterentropy" by ↵ | Mounir IDRASSI | 8 | -4/+1038 | |
Stephan Mueller as a good alternative to RDRAND (http://www.chronox.de/jent.html, smueller@chronox.de) | |||||
2019-02-08 | Windows: Add implementation of ChaCha20 based random generator. Use it for ↵ | Mounir IDRASSI | 12 | -4/+929 | |
driver need of random bytes (currently only wipe bytes but more to come later). | |||||
2019-02-01 | Windows: use CPU RDRAND or RDSEED as an additional entropy source for our ↵ | Mounir IDRASSI | 7 | -0/+519 | |
random generator when available | |||||
2019-02-01 | Fix detection of CPU features AVX2 & BMI2. Add detection of RDRAND & RDSEED ↵ | Mounir IDRASSI | 2 | -3/+41 | |
CPU features. Detect Hygon CPU as AMD one. | |||||
2019-01-30 | Help compiler optimize some crypto code on 64-bit build since x64 capable ↵ | Mounir IDRASSI | 1 | -0/+5 | |
CPUs always support SSE and SSE2 | |||||
2018-08-06 | crypto: cleaner code for Streebog carry bit handling and add comment about ↵ | Mounir IDRASSI | 1 | -5/+24 | |
missing handling of overflow caused by carry bit. | |||||
2017-11-27 | SIMD speed optimization for Kuznyechik cipher implementation (up to 2x ↵ | Mounir IDRASSI | 6 | -166/+9755 | |
speedup). Based on https://github.com/aprelev/libgost15. | |||||
2017-07-19 | Windows MBR bootloader: reduce required stack size for cascade bootloader by ↵ | Mounir IDRASSI | 1 | -0/+2 | |
removing unnecessary field from Twofish structure in this case. | |||||
2017-07-19 | Windows MBR Bootloader: workaround for 16-bit compiler internal error when ↵ | Mounir IDRASSI | 1 | -4/+4 | |
compiling Camellia source code. In GET_UINT32_BE macro, we use |= operator instead of ORing shift values. | |||||
2017-07-09 | Windows: generate pdb files for binaries in order to help investigate ↵ | Mounir IDRASSI | 1 | -4/+2 | |
crashes in the future. | |||||
2017-07-09 | Remove unnecessary code from Camellia assembly implementation that checks ↵ | Mounir IDRASSI | 2 | -71/+10 | |
for key size since we always use it with 256-bit keys. | |||||
2017-07-09 | Windows: preserve volatile registers XMM6-XMM15 in 64-bit assembly of Camellia. | Mounir IDRASSI | 1 | -512/+51 | |
2017-07-04 | Windows: correctly handle SEH exceptions during self-tests in order to ↵ | Mounir IDRASSI | 2 | -30/+41 | |
disable CPU extended features in such case. | |||||
2017-07-04 | Don't check for SSSE3 to use 64-bit SHA-512 assembly code since it uses only ↵ | Mounir IDRASSI | 1 | -0/+4 | |
SSE2 instructions. | |||||
2017-07-04 | Windows Driver: correctly save and restore extended processor state when ↵ | Mounir IDRASSI | 2 | -9/+27 | |
performing AVX operations on Windows 7 and later. Enhance readability of code handling save/restore of floating point state. | |||||
2017-07-04 | Windows: use stack instead of MMX register to save registers in 64-bit ↵ | Mounir IDRASSI | 1 | -14/+19 | |
assembly implementation of SHA-512 in order to avoid issues with the driver. | |||||
2017-07-02 | Linux/MacOSX: align workspace stack variable in WhirlpoolTransform SSE code. | Mounir IDRASSI | 1 | -1/+1 | |
2017-07-02 | Avoid alignement issues with some old compilers by using movdqu instead of ↵ | Mounir IDRASSI | 1 | -8/+8 | |
movdqa in SHA-256 SSE2 assembly. | |||||
2017-07-01 | Fix crash on machines without SSSE3 support in CPU by correctly checking for ↵ | Mounir IDRASSI | 1 | -1/+1 | |
SSSE3 before using SHA-512 SSE2 assembly which uses PSHUFB instruction. | |||||
2017-07-01 | For code logic clarity, add check for xgetbv support in CPU before using it. | Mounir IDRASSI | 1 | -1/+1 | |
2017-06-27 | Enable AVX assembly instructions only when the OS implements AVX support | Mounir IDRASSI | 1 | -2/+19 | |
2017-06-27 | Windows: use yasm define __YASM__ for compatibility with the assembly ↵ | Mounir IDRASSI | 2 | -25/+25 | |
changes done in MacOSX. | |||||
2017-06-27 | MacOSX: various changes for assembly files build. Don't use 32-bit assembly ↵ | Mounir IDRASSI | 11 | -25/+19 | |
code of SHA-512 since it is not compatible with PIE configuration of OSX compiler (absolute addressing used) | |||||
2017-06-24 | Linux/MacOSX: properly declare 64-bit constant integer values to avoid being ↵ | Mounir IDRASSI | 1 | -28/+28 | |
truncated by compiler. | |||||
2017-06-23 | Update IDRIX copyright year | Mounir IDRASSI | 2 | -2/+2 | |
2017-06-23 | Modify Aes_hw_cpu.asm to use nasm syntax that is compatible with yasm. | Mounir IDRASSI | 1 | -16/+16 | |
2017-06-23 | Crypto: Add optimized SHA-512 and SHA-256 assembly implementations for ↵ | Mounir IDRASSI | 22 | -785/+5190 | |
x86_64 and x86. This improves speed by 30%. | |||||
2017-06-21 | Windows: don't use AVX optimized Camellia in EFI bootloader until ↵ | Mounir IDRASSI | 1 | -1/+4 | |
compatibility issues are investigated | |||||
2017-06-21 | Crypto: Add optimized Camellia assembly implementation for x86_64 based on ↵ | Mounir IDRASSI | 12 | -12/+2395 | |
work by Jussi Kivilinna (https://github.com/jkivilin/supercop-blockciphers). This improve speed by a factor of 2.5 when AES-NI supported by CPU and by 30% if AES-NI not supported. | |||||
2017-06-21 | Windows: fix compilation error of assembly files after latest changes on Linux. | Mounir IDRASSI | 2 | -2/+4 | |
2017-06-13 | Linux: fix executable stack in resulting binary which was caused by crypto ↵ | Mounir IDRASSI | 5 | -0/+48 | |
assembly files missing the GNU-stack note. | |||||
2017-06-05 | cland static code analyzer fixes | kavsrf | 1 | -3/+3 | |
2017-05-22 | Windows Driver: fix "__chkstk" link error in debug build caused by some ↵ | Mounir IDRASSI | 3 | -4/+14 | |
crypto functions using too much stack space for local variables. | |||||
2017-01-12 | Fix build error in Crypto/Whirpool.c when using LLVM Clang compiler by ↵ | Mounir IDRASSI | 3 | -33/+45 | |
disabling inline assembly in this case (caused by http://llvm.org/bugs/show_bug.cgi?id=24232) | |||||
2016-12-26 | Windows: Enable Twofish optimized 64-bit assembly for UEFI bootloader since ↵ | Mounir IDRASSI | 2 | -6/+6 | |
a pre-compiled object file was included to its build system. | |||||
2016-12-07 | Windows: Don't use Twofish x64 assembly implementation for UEFI bootloader ↵ | Mounir IDRASSI | 2 | -7/+7 | |
(for now, yasm is not integrated in EDKII framework). | |||||
2016-12-07 | Windows Bootloader: fix compilation error following Twofish code changes. | Mounir IDRASSI | 1 | -3/+1 | |
2016-12-07 | Crypto: remove unnecessary alignment adjusting code in Serpent since the ↵ | Mounir IDRASSI | 1 | -46/+2 | |
SIMD implementation works with unaligned data and gain negligible compared to memcpy overhead. | |||||
2016-12-07 | Crypto: Add optimized Twofish assembly implementation for x86_64. | Mounir IDRASSI | 8 | -421/+993 | |
2016-10-17 | Implement detection of new CPU features: AVX2 and BMI2 | Mounir IDRASSI | 2 | -1/+7 | |